// `include "top_define.v"
module addr_table_mux(
	           input clk  ,
			   input rst_n,
               input studying,
               input studying1,
               input initing,
                
               input [9:0] delete_addr,
               input [71:0] delete_data,
               input delete_wren,
               output reg [71:0] delete_q,
                 
               input [9:0]  study_addr,
               input [71:0]  study_data,
               input study_wren,
               output reg [71:0]  study_q,
               output reg         q_as_en,
               output reg [9:0] table_addr,
               output reg [71:0] table_data,
               output reg table_wren,
               input [71:0] table_q
                     );
reg studying_ff1;
reg studying_ff2;

reg studying_d1;
reg studying_d2;

always @(*)
begin
	if(studying || initing) begin
	    table_addr  = study_addr;
		table_wren  = study_wren;
		table_data  = study_data;
	end
	else if(!studying) begin
	    table_addr  = delete_addr;
		table_wren  = delete_wren;
		table_data  = delete_data;
	end
	else begin
	    table_addr  = 10'd0;
		table_wren  = 1'd0;
		table_data  = 72'd0;
	end
end

always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
    studying_ff1 <= 1'b0;
    else 
    studying_ff1 <= studying1;
end
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
    studying_ff2 <= 1'b0;
    else 
    studying_ff2 <= studying_ff1;
end

always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
    studying_d1 <= 1'b0;
    else 
    studying_d1 <= studying;
end
always@(posedge clk or negedge rst_n)begin
    if(~rst_n)
    studying_d2 <= 1'b0;
    else 
    studying_d2 <= studying_d1;
end
//2021 11.3 HXF
always @(*)
begin
    if(!studying_d2)
	    delete_q = table_q;
	else
	    delete_q = 72'd0;
end

always @(*)
begin
    if(studying_ff2)begin
	    study_q = table_q;
		q_as_en = 1'b1;
	end	
	else begin
	    study_q = 72'd0;
		q_as_en  = 1'b0;
	end
end

endmodule
